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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . 5 v t o 1 2 v s y n c h r o n o u s b u c k c o n t r o l l e r f e a t u r e s w i d e o p e r a t i o n s u p p l y v o l t a g e f r o m 5 v t o 1 2 v power-on-reset monitoring on vcc excellent reference voltage regulations - 0.8v internal reference - 1% over-temperature range integrated soft-start automatic psm/pwm modes voltage mode pwm operation with 90% (max.) duty cycle under-voltage protection adjustable over-current protection threshold - sensing the r ds(on) of low-side mosfet over-voltage protection u n d e r - v o l t a g e p r o t e c t i o n simple sop-8p package lead free and green devices available (rohs compliant) a p p l i c a t i o n s g e n e r a l d e s c r i p t i o n graphic cards dsl, switch hub wireless lan notebook computer mother board lcd monitor/tv the apw8725a is a voltage mode, fixed 300khz-switch- ing frequency, and synchronous buck controller. the apw8725a allows wide input voltage that is either a single 5~12v or two supply voltage(s) for various applications. a power-on-reset (por) circuit monitors the vcc supply voltage to prevent wrong logic controls. a built-in digital soft-start circuit prevents the output voltages from over- shoot as well as limits the input current. an internal 0.8v temperature-compensated reference voltage with high accuracy is designed to meet the requirement of low out- put voltage applications. the apw8725a provides excel- lent output voltage regulations against load current variation. the controller?s over-current protection monitors the out- put current by using the voltage drops across the r ds(on) of low-side mosfet, eliminating the need for a current sensing resistor that features high efficiency and low cost. the apw8725a also integrates over-voltage protection (ovp) and under-voltage protection circuit which moni- tors the fb voltage to prevent the pwm output from over and under voltage. the apw8725a is available in a simple sop-8p package. p i n c o n f i g u r a t i o n s i m p l i f i e d a p p l i c a t i o n c i r c u i t phase fb gnd vcc lgate comp apw8725a v in v out ugate boot 5 7 6 3 4 8 2 1 on off v vcc gnd 3 ugate 2 7 comp lgate 4 6 fb 5 vcc 8 phase boot 1 9 gnd sop-8p ( t op view)
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v vcc vcc supply voltage (vcc to gnd) - 0.3 ~ 16 v v boot boot to phase voltage - 0.3 ~ 16 v > 400ns - 0.3 ~ v boot +0.3 v v ugate ugate to phase voltage < 400ns - 5 ~ v boot +5 v > 400ns - 0.3 ~ v vcc +0.3 v v lgate lgate to gnd voltage < 400ns - 5 ~ v vcc +5 v > 200ns - 0.3 ~ 16 v v phase phase to gnd voltage < 200ns - 10 ~ 30 v fb and comp to gnd (< v vcc + 0.3v) - 0.3 ~ 7 v t j maximum j unction temperature 150 c t stg storage temperature - 65 ~ 150 c t sdr maximum lead soldering t emperature, 10 seconds 260 c n o t e 1 : a b s o l u t e m a x i m u m r a t i n g s a r e t h o s e v a l u e s b e y o n d w h i c h t h e l i f e o f a d e v i c e m a y b e i m p a i r e d . e x p o s u r e t o a b s o l u t e m a x i m u m r a t i n g c o n d i t i o n s f o r e x t e n d e d p e r i o d s m a y a f f e c t d e v i c e r e l i a b i l i t y . symbol parameter typical value unit q ja thermal resistance - junction to ambient (note 2) sop - 8p 80 c /w q j c thermal resistance - junction to case sop - 8p 20 c /w t h e r m a l c h a r a c t e r i s t i c s note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. apw8725a handling code temperature range package code assembly material apw8725a ka: xxxxx - date code package code ka : sop-8p operating ambient temperature range e : -20 to 70 o c handling code tr : tape & reel assembly material g : halogen and lead free device apw8725a xxxxx
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 3 r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) symbol parameter range unit v vcc vcc supply voltage (vcc to gnd) 4.5 ~ 13.2 v v out converter output voltage 0.9 ~ 5 v v in converter input voltage 2.9 ~ v vcc v i out converter output c urrent 0 ~ 20 a t a ambient temperature - 20 ~ 70 c t j junction tempe rature - 2 0 ~ 1 25 c e l e c t r i c a l c h a r a c t e r i s t i c s apw 8725a symbol parameter test condition s min. typ. max. unit input supply voltage and current vcc supply current (shutdown mode) ugate and lgate open; comp=gnd - 4 6 i vcc vcc supply current ugate and lgate open - 16 24 m a power - on - reset (p or) rising vcc por threshold 3.7 4.1 4.4 v vcc por hysteresis 0.3 0.45 0.6 v oscillator f osc oscillator frequency 270 300 330 khz d v osc oscillator sawtooth amplitude (note 4) - 1.5 - v d max maximum duty cycle 85 - 90 % error amplifier v ref reference voltage t a = - 20 ~ 70 c 0.792 0.8 0.808 v converter load regulation (note 4) i out = 2 ~ 12a - - 0.2 % gm transconductance - 667 - m a/v fb input leakage current v fb = 0.8v - 0.1 1 m a comp high voltage r l = 10k w to gnd - 2.5 - comp low voltage r l = 10k w to gnd - 1 - v maximum comp source current v comp = 2v - 200 - maximum comp sink current v comp = 2v - 200 - m a gate dri vers high - side gate driver source current v boot = 12v, v ugate - phase = 2v - 1.8 - a high - side gate driver s ink impedance boot = 12v, i ugate = 0.1a - 2.3 - w low - side gate driver source current v vcc = 1 2 v , v lgate = 2v - 1.8 - a low - side gate driver s ink impedance v vcc = 12v, i ugate = 0.1a - 1.3 - w t d dead - time ( note 4) - 30 - ns refer to the typical application circuit. these specifications apply over v vcc = 12v, t a = -20c to 70c, unless otherwise noted. typical values are at t a = 25c. n o t e 3 : r e f e r t o t h e a p p l i c a t i o n c i r c u i t f o r f u r t h e r i n f o r m a t i o n .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) refer to the typical application circuit. these specifications apply over v vcc = 12v, t a = -20c to 70c, unless otherwise noted. typical values are at t a = 25c. apw 8725a symbol parameter test condition s min. typ. max. unit p rotections v fb_uv fb under - voltage protection trip point percentage of v ref 45 50 55 % v fb_ov fb over - voltage protection trip point v fb rising 115 120 125 % fb over - voltage prote ction hysteresis - 5 - % v ocp_max built - in maximum ocp voltage 300 - - mv i ocset ocset current source 19.5 21.5 23.5 m a soft - start v disable shutdown threshold of v comp - - 0.6 v t ss internal soft - start interval (note 4) - 1.7 - ms n o t e 4 : g u a r a n t e e d b y d e s i g n , n o t p r o d u c t i o n t e s t e d .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 5 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 2 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . e n a b l e ch1: v comp , 1v/div ch2: v out , 500mv/div ch3: v phase , 10v/div time: 500 m s/div v phase 1 3 2 v out v comp s h u t d o w n ch1: v comp , 1v/div ch2: v out , 500mv/div ch3: v phase , 10v/div time: 1m s/div 1 3 2 r load = 10 w v comp v out v phase p o w e r o n p o w e r o f f ch1: v in , 5v/div ch2: v out , 500mv/div ch3: v ugate , 10v/div time: 1m s/div 1 3 2 v in v out v u gate ch1: v in , 5v/div ch2: v out , 500mv/div ch3: v ugate , 10v/div time: 200m s/div 1 3 2 v in v out v u gate
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 6 o p e r a t i n g w a v e f o r m s ( c o n t . ) r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 2 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . u g a t e f a l l i n g u g a t e r i s i n g 1 , 2 3 v ugate2 v lgate2 v phase2 ch1: v ugate , 20v/div ch2: v lgate , 10v/div ch3: v phase , 10v/div time: 20n s/div ch1: v ugate , 20v/div ch2: v lgate , 10v/div ch3: v phase , 10v/div time: 20n s/div 2 3 v lgate 1 v ugate v phase p s m t o p w m p w m t o p s m ch1: v out , 500mv/div time: 500 m s/div ch2: v phase , 10v/div ch3: i l , 2a/div ch1: v out , 1v/div time: 500 m s/div ch2: v phase , 10v/div ch3: i l , 2a/div 2 3 1 v out i out =10ma to 2a v phase i l 2 3 1 v out v phase i l i out =2a to 10ma
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 7 o p e r a t i n g w a v e f o r m s ( c o n t . ) r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 2 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . l o a d t r a n s i e n t r e s p o n s e o v e r - c u r r e n t p r o t e c t i o n 3 1 2 v out v phase i l r ocset =5.1k w , r ds (low-side)=10m w ch1: v out , 500mv/div time: 5 m s/div ch2: v phase , 20a/div ch3: i l , 10a/div ch1: v out , 500mv/div time: 50 m s/div ch2: v phase , 20a/div ch3: i l , 10a/div 3 1 2 v out v phase i l o v e r - c u r r e n t p r o t e c t i o n ch1: v out , 50mv/div time: 100 m s/div ch2: i out , 5a/div v out i out i out slew rate=10a/ m s i out =10ma->10a->10ma 1 2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 8 p i n d e s c r i p t i o n pin no. name function 1 boot this pin provides the bootstrap voltage to the high - side gate driver for driving the n - channel mosfet. an external capacitor from phase to boot, an internal diode, and the power supply v o ltage vcc, generates the bootstrap vo ltage for the high - side gate d r iver (ugate). 2 ugate high - side g ate dr iver output. this pin is the gate driver for high - side mosfet. 3 gnd signal and power ground. connecting this pin to system ground. 4 lgate low - side gate driver output and over - curren t setting input. this pin is the gate driver for low - side mosfet. it also used to set the maximum inductor current. refer to the section in ? function description ? for detail. 5 vcc power s upply i nput for control circuitry . connect a nominal 5v to 12v powe r supply voltage to this pin. a power - on - reset function monitors the input voltage at this pin. it is recommended that a decoupling capacitor (1 to 10 m f) be connected to gnd for noise decoupling. 6 fb feedback i nput of converter . the converter senses feedback voltage via fb and regulate s the fb voltage at 0.8v. connecting fb with a resistor - divider from the output set s the output voltage of the convert er . 7 comp this is a multiplexed pin. during the soft - start and normal converter operation, this pin represents the output of the error amplifier. it is used to compensate the regulation control loop in combination with the fb pin . pulling comp low (v disa ble = 0. 6 v typical) will shut down the controller . when the pull - down device is released, the comp pin will start to rise. when the comp pin rises above the v disable trip point, the apw8725a will begin a new i nitialization and soft - start cycle. 8 phase th is pin is the return path for the high - side gate driver. connect ing this pin to the high - side mosfet source and connect ing a capacitor to boot for the bootstrap voltage. this pin is also used to monitor the voltage drop across the low - side mosfet for o ver - current protection. 9 ( exposed pad ) gnd thermal pad. connect this pad to the system ground plan for good thermal conductivity. t y p i c a l a p p l i c a t i o n c i r c u i t phase fb gnd vcc lgate comp apw8725a c in2 470 f x 2 c in1 1 f l1 1 h v in v out ugate c out 470 f x 2 vcc supply (5~12v) boot r1 1k w r2 2k w 5 7 6 3 4 8 2 1 r5 2r2 c5 1 f c1 15nf r3 15k w c2 15pf q1 apm2510 q2 apm2556 on off c4 0.1 f r ocset q3 2n7002
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 9 b l o c k d i a g r a m power-on- reset sample and hold to lgate v rocset soft - start and fault logic gate control 2xv rocset sense low side error amplifier v ref oscillator pwm comparator uvp comparator regulator 3v v ref (0.8v typical) izcmp phase ugate boot comp gnd fb vcc soft- s tart inhibit i ocset (21.5 m a typical) lgate ovp comparator 1.2 1/2 0.6v disable vcc 0.8v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 0 f u n c t i o n d e s c r i p t i o n power-on-reset (por) soft-start over-current protection the power-on-reset (por) function of apw8725a con- tinually monitors the input supply voltage (vcc) and en- sures that the ic has sufficient supply voltage and can work well. the por function initiates a soft-start process while the vcc voltage exceeds the por threshold; the por function also inhibits the operations of the ic while the vcc voltage falls below the por threshold. the apw8725a builds in a 40-steps digital soft-start to control the output voltage rise as well as limit the current surge at the start-up. during soft-start, the internal step voltage connected to the one of the positive inputs of the error amplifier replaces the reference voltage (0.8v typical) until the step voltage reaches the reference voltage. the digital soft-start circuit interval (shown as figure 1) de- pends on the switching frequency. the over-current function protects the switching converter against over-current or short-circuit conditions. the con- troller senses the inductor current by detecting the drain- to-source voltage which is the product of the inductor?s current and the on-resistance of the low-side mosfet during on-state. a resistor (r ocset ), connected from the lgate to the gnd, programs the over-current trip level. before the ic ini- tiates a soft-start process, an internal current source, i ocset (21.5 m a typical), flowing through the r ocset develops a voltage (v rocset ) across the r ocset . during the normal operation, the device holds v rocset and stops the current source, i ocset . when the voltage across the low-side mosfet exceeds the double v rocset (2 x v rocset ), the ic shuts off the converter and then initiates a new soft-start process. after 2 over-current events are counted, the de- vice is shut down and all the gate drivers (ugate, lgate, and drive) are off. both the output of the pwm converter and linear controller are latched to be floating. the apw8725a has an internal ocp voltage, v ocp_max , and the value is 0.3v minimum. when the r ocset x i ocset exceeds 0.3v or the r ocset is floating or not connected, the v rocset will be the default value 0.3v. the over current threshold would be 0.7v across low-side mosfet. the threshold of the valley inductor current-limit is therefore given by: ) side low ( r r i 2 i ) on ( ds ocset ocset limit - = for the over-current is never occurred in the normal oper- ating load range; the variation of all parameters in the above equation should be considered: - the r ds(on) of low-side mosfet is varied by tempera- ture and gates to source voltage. users should deter- mine the maximum r ds(on) by using the manufacturer?s datasheet. - the minimum i ocset (19.5 m a) and minimum r ocset should be used in the above equation. - note that the i limit is the current flow through the low- side mosfet; i limit must be greater than valley inductor current which is output current minus the half of inductor ripple current. 2 i i i ) max ( out limit d - > where d i = output inductor ripple current - the overshoot and transient peak current also should be considered. voltage(v) time v vcc v out por t 2 t 0 t 3 t 1 ocset count completed ocset count start (ocset duration, t 2 - t 1 , less than 0.9ms) f i g u r e 1 . s o f t - s t a r t i n t e r v a l ( ) 512 f 1 t t t osc 2 3 ss = - =
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 1 under-voltage protection o v e r - v o l t a g e p r o t e c t i o n ( o v p ) s h u t d o w n a n d e n a b l e pulse skipping mode (psm) a d a p t i v e s h o o t - t h r o u g h p r o t e c t i o n the under-voltage function monitors the voltage on fb (v fb ) by under-voltage (uv) comparator to protect the pwm converter against short-circuit conditions. when the v fb falls below the falling uvp threshold (50% v ref ), a fault signal is internally generated and the device turns off high-side and low-side mosfets. the converter is shut- down and the output is latched to be floating. the over-voltage protection monitors the fb voltage to prevent the output from over-voltage condition. when the output voltage rises above 120% of the nominal output voltage, the apw8725a turns off the high-side mosfet and turns on the low-side mosfet until the output volt- age falls below the falling ovp threshold, regulating the output voltage around the ovp threshold. the apw8725a can be shut down or enabled by pulling low the voltage on comp. the comp is a dual-function pin. during normal operation, this pin represents the output of the error amplifier. it is used to compensate the regulation control loop in combination with the fb pin. pulling the comp low (v disable = 0.6v typical) places the controller into shutdown mode which ugate and lgate are pulled to phase and gnd respectively. when the pull-down device is released, the comp volt- age will start to rise. when the comp voltage rises above the v disable threshold, the apw8725a will begin a new initialization and soft-start process. at light loads, the inductor current may reach zero or re- verse on each pulse. the low-side mosfet is turned off by the current reversal comparator, izcmp, to block the negative inductor current. in this condition, the converter enters discontinuous current mode operation. at very light loads, the apw8725a will automatically skip pulses in pulse skipping mode operation to reduce switching losses as well as maintain output regulation for efficient applications. the gate drivers incorporate an adaptive shoot-through protection to prevent high-side and low-side mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to rise. during turn-off of the low-side mosfet, the lgate volt- age is monitored until it is below 1.5v threshold, at which time the ugate is released to rise after a constant delay. during turn-off of the high-side ocsfet, the ugate-to- phase voltage is also monitored until it is below 1.5v threshold, at which time the lgate is released to rise after a constant delay. f u n c t i o n d e s c r i p t i o n ( c o n t . )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 2 a p p l i c a t i o n i n f o r m a t i o n o u t p u t c a p a c i t o r s e l e c t i o n t h e s e l e c t i o n o f c o u t i s d e t e r m i n e d b y t h e r e q u i r e d e f f e c - t i v e s e r i e s r e s i s t a n c e ( e s r ) a n d v o l t a g e r a t i n g r a t h e r t h a n t h e a c t u a l c a p a c i t a n c e r e q u i r e m e n t . t h e r e f o r e , s e l e c t i n g h i g h p e r f o r m a n c e l o w e s r c a p a c i t o r s i s i n t e n d e d f o r s w i t c h i n g r e g u l a t o r a p p l i c a t i o n s . i n s o m e a p p l i c a t i o n s , m u l t i p l e c a p a c i t o r s h a v e t o b e p a r a l l e l e d t o a c h i e v e t h e d e s i r e d e s r v a l u e . i f t a n t a l u m c a p a c i t o r s a r e u s e d , m a k e s u r e t h e y a r e s u r g e t e s t e d b y t h e m a n u f a c t u r e s . i f i n d o u b t , c o n s u l t t h e c a p a c i t o r s m a n u f a c t u r e r . i n p u t c a p a c i t o r s e l e c t i o n t h e i n p u t c a p a c i t o r i s c h o s e n b a s e d o n t h e v o l t a g e r a t i n g a n d t h e r m s c u r r e n t r a t i n g . f o r r e l i a b l e o p e r a t i o n , s e l e c t t h e c a p a c i t o r v o l t a g e r a t i n g t o b e a t l e a s t 1 . 3 t i m e s h i g h e r t h a n t h e m a x i m u m i n p u t v o l t a g e . t h e m a x i m u m r m s c u r r e n t r a t i n g r e q u i r e m e n t i s a p p r o x i m a t e l y i o u t / 2 w h e r e i o u t i s t h e l o a d c u r r e n t . d u r i n g p o w e r u p , t h e i n p u t c a p a c i - t o r s h a v e t o h a n d l e l a r g e a m o u n t o f s u r g e c u r r e n t . i f t a n t a - l u m c a p a c i t o r s a r e u s e d , m a k e s u r e t h e y a r e s u r g e t e s t e d b y t h e m a n u f a c t u r e s . i f i n d o u b t , c o n s u l t t h e c a p a c i t o r s m a n u f a c t u r e r . f o r h i g h f r e q u e n c y d e c o u p l i n g , a c e r a m i c c a p a c i t o r b e - t w e e n 0 . 1 m f t o 1 m f c a n c o n n e c t b e t w e e n v c c a n d g r o u n d p i n . i n d u c t o r s e l e c t i o n t h e i n d u c t a n c e o f t h e i n d u c t o r i s d e t e r m i n e d b y t h e o u t - p u t v o l t a g e r e q u i r e m e n t . t h e l a r g e r t h e i n d u c t a n c e , t h e l o w e r t h e i n d u c t o r ? s c u r r e n t r i p p l e . t h i s w i l l t r a n s l a t e i n t o l o w e r o u t p u t r i p p l e v o l t a g e . t h e r i p p l e c u r r e n t a n d r i p p l e v o l t a g e c a n b e a p p r o x i m a t e d b y : w h e r e f s i s t h e s w i t c h i n g f r e q u e n c y o f t h e r e g u l a t o r . d v o u t = i r i p p l e x e s r a t r a d e o f f e x i s t s b e t w e e n t h e i n d u c t o r ? s r i p p l e c u r r e n t a n d t h e r e g u l a t o r l o a d t r a n s i e n t r e s p o n s e t i m e . a s m a l l e r i n - d u c t o r w i l l g i v e t h e r e g u l a t o r a f a s t e r l o a d t r a n s i e n t r e - s p o n s e a t t h e e x p e n s e o f h i g h e r r i p p l e c u r r e n t a n d v i c e v e r s a . t h e m a x i m u m r i p p l e c u r r e n t o c c u r s a t t h e m a x i - m u m i n p u t v o l t a g e . a g o o d s t a r t i n g p o i n t i s t o c h o o s e t h e r i p p l e c u r r e n t t o b e a p p r o x i m a t e l y 3 0 % o f t h e m a x i m u m o u t p u t c u r r e n t . o n c e t h e i n d u c t a n c e v a l u e h a s b e e n c h o s e n , s e l e c t i n g a n i n d u c t o r i s c a p a b l e o f c a r r y i n g t h e r e q u i r e d p e a k c u r - r e n t w i t h o u t g o i n g i n t o s a t u r a t i o n . i n s o m e t y p e s o f i n d u c t o r s , e s p e c i a l l y c o r e t h a t i s m a k e o f f e r r i t e , t h e r i p p l e c u r r e n t w i l l i n c r e a s e a b r u p t l y w h e n i t s a t u r a t e s . t h i s w i l l r e s u l t i n a l a r g e r o u t p u t r i p p l e v o l t a g e . c o m p e n s a t i o n t h e o u t p u t l c f i l t e r o f a s t e p d o w n c o n v e r t e r i n t r o d u c e s a d o u b l e p o l e , w h i c h c o n t r i b u t e s w i t h - 4 0 d b / d e c a d e g a i n s l o p e a n d 1 8 0 d e g r e e s p h a s e s h i f t i n t h e c o n t r o l l o o p . a c o m p e n s a t i o n n e t w o r k b e t w e e n c o m p p i n a n d g r o u n d s h o u l d b e a d d e d . t h e s i m p l e s t l o o p c o m p e n s a t i o n n e t - w o r k i s s h o w n i n f i g u r e 5 . t h e o u t p u t l c f i l t e r c o n s i s t s o f t h e o u t p u t i n d u c t o r a n d o u t p u t c a p a c i t o r s . t h e t r a n s f e r f u n c t i o n o f t h e l c f i l t e r i s g i v e n b y : t h e p o l e s a n d z e r o o f t h i s t r a n s f e r f u n c t i o n a r e : t h e f l c i s t h e d o u b l e p o l e s o f t h e l c f i l t e r , a n d f e s r i s t h e z e r o i n t r o d u c e d b y t h e e s r o f t h e o u t p u t c a p a c i t o r . output voltage selection the output voltage can be programmed with a resistive divider. use 1% or better resistors for the resistive divider is recommended. the fb pin is the inverter input of the error amplifier , and the reference voltage is 0.8v . the output voltage is determined by: ? ? ? ? ? + = 2 1 out r r 1 0.8 v where r1 is the resistor connected from v out to fb and r 2 is the resistor connected from fb to the gnd. in out sw out in ripple v v l f v v i - = 1 c esr s c l s c esr s 1 out out 2 out + + + = gain lc out c l p 2 1 = f lc out c esr p 2 1 = f esr
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 3 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) f i g u r e 3 . t h e l c f i l t e r g a i n & f r e q u e n c y t h e p w m m o d u l a t o r i s s h o w n i n f i g u r e 4 . t h e i n p u t i s t h e o u t p u t o f t h e e r r o r a m p l i f i e r a n d t h e o u t p u t i s t h e p h a s e n o d e . t h e t r a n s f e r f u n c t i o n o f t h e p w m m o d u l a t o r i s g i v e n b y : f i g u r e 4 . t h e p w m m o d u l a t o r t h e c o m p e n s a t i o n c i r c u i t i s s h o w n i n f i g u r e 5 . r 3 a n d c 1 i n t r o d u c e a z e r o a n d c 2 i n t r o d u c e s a p o l e t o r e d u c e t h e s w i t c h i n g n o i s e . t h e t r a n s f e r f u n c t i o n o f e r r o r a m p l i - f i e r i s g i v e n b y : t h e p o l e a n d z e r o o f t h e c o m p e n s a t i o n n e t w o r k a r e : c o m p e n s a t i o n ( c o n t . ) f i g u r e 5 . c o m p e n s a t i o n n e t w o r k t h e c l o s e d l o o p g a i n o f t h e c o n v e r t e r c a n b e w r i t t e n a s : f i g u r e 6 s h o w s t h e c o n v e r t e r g a i n a n d t h e f o l l o w i n g g u i d e - l i n e s w i l l h e l p t o d e s i g n t h e c o m p e n s a t i o n n e t w o r k . 1 . s e l e c t t h e d e s i r e d z e r o c r o s s o v e r f r e q u e n c y f o : ( 1 / 5 ~ 1 / 1 0 ) x f s w > f o > f z u s e t h e f o l l o w i n g e q u a t i o n t o c a l c u l a t e r 3 : f esr f lc frequency -40db/dec -20db/dec gain gm f r2 r2 r1 2 f f v v r3 o lc esr in osc + d = figure 2. the output lc filter l c out esr output phase osc in pwm v v = gain d c2 c2 c1 r3 c2 c1 s s c1 r3 1 s gm + + + = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = = sc2 1 // sc1 1 r3 gm gm o amp z gain c2 c1 c2 c1 r3 2 1 + p p f c1 r3 2 1 p = f z c2 v out r2 r1 r3 error amplifier v ref c1 comp fb - + amp pwm lc gain gain gain + r2 r1 r2 w h e r e : g m = 6 6 7 m a / v v osc pwm comparator driver driver output of error amplifier v in phase
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 4 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) c o m p e n s a t i o n ( c o n t . ) f i g u r e 6 . c o n v e r t e r g a i n & f r e q u e n c y m o s f e t s e l e c t i o n t h e s e l e c t i o n o f t h e n - c h a n n e l p o w e r m o s f e t s i s d e t e r - m i n e d b y t h e r d s ( o n ) , r e v e r s e t r a n s f e r c a p a c i t a n c e ( c r s s ) , a n d m a x i m u m o u t p u t c u r r e n t r e q u i r e m e n t . t h e l o s s e s i n t h e m o s f e t s h a v e t w o c o m p o n e n t s : c o n d u c t i o n l o s s a n d t r a n s i t i o n l o s s . f o r t h e u p p e r a n d l o w e r m o s f e t , t h e l o s s e s a r e a p p r o x i m a t e l y g i v e n b y t h e f o l l o w i n g e q u a t i o n s : p u p p e r = i o u t 2 ( 1 + t c ) ( r d s ( o n ) ) d + ( 0 . 5 ) ( i o u t ) ( v i n ) ( t s w ) f s w p l o w e r = i o u t 2 ( 1 + t c ) ( r d s ( o n ) ) ( 1 - d ) w h e r e i o u t i s t h e l o a d c u r r e n t t c i s t h e t e m p e r a t u r e d e p e n d e n c y o f r d s ( o n ) f s w i s t h e s w i t c h i n g f r e q u e n c y t s w i s t h e s w i t c h i n g i n t e r v a l d i s t h e d u t y c y c l e n o t e t h a t b o t h m o s f e t s h a v e c o n d u c t i o n l o s s e s w h i l e t h e u p p e r m o s f e t i n c l u d e s a n a d d i t i o n a l t r a n s i t i o n l o s s . t h e s w i t c h i n g i n t e r n a l , t s w , i s t h e f u n c t i o n o f t h e r e v e r s e t r a n s f e r c a p a c i t a n c e c r s s . f i g u r e 7 i l l u s t r a t e s t h e s w i t c h - i n g w a v e f o r m i n t e r n a l o f t h e m o s f e t . t h e ( 1 + t c ) t e r m f a c t o r s i n t h e t e m p e r a t u r e d e p e n d e n c y o f t h e r d s ( o n ) a n d c a n b e e x t r a c t e d f r o m t h e ? r d s ( o n ) v s t e m - p e r a t u r e ? c u r v e o f t h e p o w e r m o s f e t . 1 f c1 r3 c1 c2 sw - p = layout consideration in any high switching frequency converter, a correct lay- out is important to ensure proper operation of the regulator. with power devices switching at 300khz,the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the pwm mosfet. before turn-off, the mosfet is car- rying the full load current. during turn-off, current stops flowing in the mosfet and is free-wheeling by the lower mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short and wide printed circuit traces should minimize interconnecting imped- f i g u r e 7 . s w i t c h i n g w a v e f o r m a c r o s s m o s f e t 2 . p l a c e t h e z e r o f z b e f o r e t h e l c f i l t e r d o u b l e p o l e s f l c : f z = 0 . 7 5 x f l c c a l c u l a t e t h e c 1 b y t h e e q u a t i o n : 3 . s e t t h e p o l e a t t h e h a l f t h e s w i t c h i n g f r e q u e n c y : f p = 0 . 5 x f s w c a l c u l a t e t h e c 2 b y t h e e q u a t i o n : lc f 0.75 r1 2 1 c1 p = f lc f esr f p =0.5f sw f z =0.75f lc f o frequency pwm & filter gain compensation gain converter gain gain 20 . log(gm . r3) d v osc v in 20 . log v o l t a g e a c r o s s d r a i n a n d s o u r c e o f m o s f e t time v ds t sw
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 5 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) layout consideration (cont.) figure 8. layout guidelines - keep the switching nodes (ugate, lgate, and phase) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible. - the traces from the gate drivers to the mosfets (ug and lg) should be short and wide. - place the source of the high-side mosfet and the drain of the low-side mosfet as close as possible. minimiz- ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be close their pins. (for example, place the decoupling ceramic capacitor near the drain of the high-side mosfet as close as possible. the bulk capacitors are also placed near the drain). - the input capacitor should be near the drain of the up- per mosfet; the output capacitor should be near the loads. the input capacitor gnd should be close to the output capacitor gnd and the lower mosfet gnd. - the drain of the mosfets (v in and phase nodes) should be a large plane for heat sinking. - the r ocset resistance should be placed near the ic as close as possible. ances and the magnitude of voltage spike. and signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. figure 8. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. components along the bold lines should be placed lose together. below is a checklist for your layout: vcc boot phase ugate lgate v in v out l o a d apw8725a r ocset close to ic
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 6 p a c k a g e i n f o r m a t i o n s o p - 8 p thermal pad d d1 e 2 e 1 e e b a 2 a a 1 view a l 0 . 2 5 gauge plane seating plane q note : 1. followed from jedec ms-012 ba. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. dimension "e" does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. 0.020 0.010 0.020 0.050 0.006 0.063 max. 0.40 l q 0 o c e e h e1 0.25 d c b 0.17 0.31 0.016 1.27 8 o c 0 o c 8 o c 0.50 1.27 bsc 0.51 0.25 0.050 bsc 0.010 0.012 0.007 millimeters min. s y m b o l a1 a2 a 0.00 1.25 sop-8p max. 0.15 1.60 min. 0.000 0.049 inches d1 2.50 0.098 2.00 0.079 e2 3.50 3.00 0.138 0.118 4.80 5.00 0.189 0.197 3.80 4.00 0.150 0.157 5.80 6.20 0.228 0.244 h x 4 5 o c see view a -t- seating plane < 4 mils
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 7 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 so p - 8p 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.4 0 6.40 ? 0.20 5.20 ? 0.20 2.10 ? 0.20 c a r r i e r t a p e & r e e l d i m e n s i o n s d e v i c e s p e r u n i t ( m m ) package type unit quantity sop - 8 p tape & reel 2500 h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 8 t a p i n g d i r e c t i o n i n f o r m a t i o n s o p - 8 p user direction of feed c l a s s i f i c a t i o n p r o f i l e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 1 9 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c r e l i a b i l i t y t e s t p r o g r a m test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - a u g . , 2 0 1 0 a p w 8 7 2 5 a w w w . a n p e c . c o m . t w 2 0 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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